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preliminary TTP229-FSD tontouch tm 09?/12/22 page 1 of 14 ver : 1.1 8 keys touch pad detector ic general description the TTP229-FSD tontouch tm ic is capacitive sensing design sp ecifically for touch pad controls. the device built in regulator for touch sensor. stab le sensing method can cover diversity conditions. human interfaces control panel links through non-conducti ve dielectric material. the main application is focused at replacing of the mechanical switch or button. the assp can i ndependently handle the 8 touch pads. features ? operating voltage 2.4v~5.5v ? built-in regulator ? stand-by current at 3v, and sleep mode slow sampling rate 8hz => typical 2.0ua ? provides i 2 c-bus slave interface ? offer multi-key or single-key feature by option ? provides two kinds of sampling ra te that slow sampling rate 8hz and fast sampling rate 64hz at sleep mode ? have the maximum key-on time about 80sec by pin option ? sensitivity can adjust by the capacitance(1~50pf) outside ? after power-on have about 0.5sec stable-time, during the time do not touch the key pa d, and all functions are disabled ? auto calibration for environment changing and the re-calibration period is about 4.0sec, wh en all keys are not activated for fixed time application ? wide consumer products ? button key replacement
preliminary TTP229-FSD tontouch tm 09?/12/22 page 2 of 14 ver : 1.1 block diagram control circuit sda scl i2c-bus interface a2 a1 a0 test control circuit wake-up detecing slpsena system power on circuit system oscillator circuit circuit function control and and key scanning timing counter circuit regulator control circuit function option circuit detecting and sense port tp7 tp6 tp5 tp4 senadj1 tp3 tp2 tp1 tp0 senadj0 package configuration scl sda tp0 tp1 senadj0 tp2 tp3 a0 a1 a2 tp7 test vss slpsena 10 9 8 7 6 5 4 3 2 1 11 12 13 14 20 19 18 17 16 15 (ssop-20) ttp229-f tp6 vdd tp4 tp5 senadj1
preliminary TTP229-FSD tontouch tm 09?/12/22 page 3 of 14 ver : 1.1 pin description pin no. pin name share pin i/o type pin description 1 vss p negative power supply, ground 2 slpsena i/o sleep mode sensitiv ity adjustment pin for group-a(tp0~7) 3 tp3 skms1 i/o touch pad input pin(key-3) key action function option- 1(single-key/multi-key) default is all single-key 4 tp2 i/o touch pad input pin(key-2) 5 senadj0 i/o touch pad tp0~3 sensitivity adjust common pin 6 tp1 i/o touch pad input pin(key-1) 7 tp0 i/o touch pad input pin(key-0) 8 sda i/od data pin for the i 2 c-bus serial data interface 9 nc 10 scl i serial cloc k input pin for the i 2 c-bus serial interface 11 test i-pl only for test 12 a2 i-ph a2~0 are input pins for the i 2 c-bus device address selection 13 a1 i-ph a2~0 are input pins for the i 2 c-bus device address selection 14 a0 i-ph a2~0 are input pins for the i 2 c-bus device address selection 15 tp7 sksrt i/o touch pad input pin(key-7) maximum key-on time function option(infinite/80sec) default is infinite 16 tp6 slwptm i/o touch pad input pin(key-6) sleep mode sampling length function option(4.0/2.0ms) default is 4.0ms 17 senadj1 i/o touch pad tp4~7 sensitivity adjust common pin 18 tp5 wpsct i/o touch pad input pin(key-5) sampling rate at sleep mode function option(8hz/64hz) default is 8hz 19 tp4 skms0 i/o touch pad input pin(key-4) key action function option- 0(single-key/multi-key) default is all single-key 20 vdd p positive power supply note pin type i cmos input only i-ph cmos input and pull-high resister i-pl cmos input and pull-low resister o cmos push-pull output i/o cmos i/o p power / ground od cmos open drain output
preliminary TTP229-FSD tontouch tm 09?/12/22 page 4 of 14 ver : 1.1 electrical characteristics ? absolute maximum ratings ? dc/ac characteristics (test condition at room temperature=25 ) parameter symbol conditions value unit operating temperature t op -40 ~ +85 storage temperature t stg -50 ~ +125 power supply voltage vdd ta=25 c vss-0.3 ~ vss+6.0 v input voltage v in ta=25 c vss-0.3 to vdd+0.3 v human body mode esd 6 kv note vss symbolizes for system ground parameter symbol test condition min. typ. max. unit operating voltage vdd 2.4 - 5.5 v internal regulator output vreg 2.2 2.3 2.4 v operating current (no load) i op vdd=3.0v 20 ua sampling rate 8hz 2.0 stand-by current (vdd=3.0v) (sampling length 4.0ms) i sd sampling rate 64hz 5.5 ua input ports v il input low voltage 0 - 0.2 vdd input ports v ih input high voltage 0.8 - 1.0 vdd output port sink current i ol vdd=3v, v ol =0.6v - 8 - ma output port source current i oh vdd=3v, v oh =2.4v - -4 - ma vdd=3v, sampling rate 8hz 125 ms wake-up response time (at sleep mode) t wu vdd=3v, sampling rate 64hz 15.6 ms output response time (at operation) t r vdd=3v 16 ms maximum key-on time t mot 50 80 110 sec input pin pull-high resistor (a0~a2) r ph vdd=3v, 30k ohm input pin pull-low resistor (test) r pl vdd=3v 30k ohm
preliminary TTP229-FSD tontouch tm 09?/12/22 page 5 of 14 ver : 1.1 function description 1. sensitivity adjustment the total loading of electrode size and capacitance of connecti ng line on pcb can affect the sensitivity. so the sensitivity adjustment must according to the practical application on pcb. the TTP229-FSD offers some methods for adjusting the sensitivity outside. 1-1 by the electrode size under other conditions are fixed. using a larger el ectrode size can increase sensitivity. otherwise it can decrease sensitivity. but the electrode size must use in the effective scope. 1-2 by the panel thickness under other conditions are fixed. using a thinner panel can increase sensitivity. otherwise it can decrease sensitivity. but the panel thickness must be below the maximum value. 1-3 by the value of external capacito r (please see the down figure 1-3-1) under other conditions are fixed. when adding the values of cj0~cj1 and cjwa will reduce sensitivity in the useful range (1pf Q cj0~cj1 Q 50pf, 1pf Q cjwa Q 50pf). when do not use any capacitor that means open on the position of capaci tor, the sensitivity is most sensitive. the capacitors cj0~cj1 are used to adjust the sensit ivity of keys at opera tion mode. the capacitors cjwa is used to adjust the wake -up sensitivity at sleep mode. about the relation of capacito r and controlled keys pl ease to see below table. the capacitor the keys-group controlled and adjusted cj0 k0~k3 group cj1 k4~k7 group cjwa k0~k7 group note when using the value of capacitor to adjust the sensitivity, recommending to adjust the cj0~cj1 capacitor for k0~k7 first, then adjusti ng the cjwa capacitor for wake-up sensitivity. a0 a1 a2 scl sda test electrode cjwa slpsena k7 k6 k5 k4 cj1 vss senadj0 tp0 tp7 tp6 tp5 tp4 tp3 tp2 tp1 vdd senadj1 cj0 k3 k2 k1 k0 figure 1-3-1
preliminary TTP229-FSD tontouch tm 09?/12/22 page 6 of 14 ver : 1.1 2. input keys number the TTP229-FSD has only 8 keys input mode. 3. output mode the TTP229-FSD only has i 2 c-bus slave interface mode. at the mode the sda pin is a serial data pin, th e scl is a serial clock input pin. the sda and scl pins must be pulled-high w ith an external resistor. and the 4-bits identify code for the TTP229-FSD is (1010) . the device address is defined by the state of the a0, a1 and a2 pins. th e three pins have pull-hi gh resistor internal, can be set to 0 external. the TTP229-FSD 8-bits slave device address includes 4-bits identifie r, 3-bits option address and r/w bit (see the table 3-1). the TTP229-FSD ic uses the i 2 c-bus slave interface data transmission protocol to output the data of the touch pads (tp0~tp7 pins), so the TTP229-FSD only accepts the read operation that r/w bit is 1 . if it is 0 , the TTP229-FSD will not respond the write operation. otherwise, the i 2 c-bus slave interface of TTP229-FSD conf orms to the communication protocols. it supports the fast mode that the maximum scl clock frequency is 400khz. the i 2 c-bus slave interface supports the following communication protocols: bus not busy : the sda and the scl lines remain high level when the bus is not active. start condition : start condition is sda 1 to 0 transition when scl=1.(see figure 3-2) stop condition : stop condition is sda 0 to 1 tran sition when scl=1.(see figure 3-2) data valid : following a start condition, th e data on the sda line must be stable during the high period of scl. the high or low state of the data line can only change when the clock signal on the scl line is low.(see figure 3-2) ack (acknowledge) : an ack signal indicates that a data tr ansfer is completed successfully. the transmitter (the master or the slave) releases the bus after transmitting eight bits. during the ninth clock, which the master generates, the receiver pulls the sda line low to acknowledge that it successfully received the eight bits of data. bu t the slave does not send an ack if it does not successfully received the eight bits of data. in data read operations, the slave releases the sd a line after transmitting 8 bits of data and then monitors the line for an ack signal during the nint h clock period. if an ack is detected, the slave will continue to transmit next data. if an ack is not detected, the slave terminates data transmission and waits for a stop condition to be issued by the master before returning to its stand-by mode. slave address : the identify code for the TTP229-FSD is (1010) . the device address can be set by the state of the a2, a1 and a0 pins. read/write : the final (eighth) bit of th e slave address defines the type of operation to be performed. if the r/w bit is 1 , a read operation is executed. if it is 0 , a write operation is executed. but the TTP229-FSD only accepts read operation. the sequence of read data operation please see figure 3-1. table 3-1. slave device addressing device identifier device address r/w bit device b7 b6 b5 b4 b3 b2 b1 b0 TTP229-FSD 1 0 1 0 a2 a1 a0 r
preliminary TTP229-FSD tontouch tm 09?/12/22 page 7 of 14 ver : 1.1 from master not ack from slave ack stop data_0 start slave address b0 b1 b2 b3 b4 b5 b6 b7 r a0 a1 a2 note : data_0 : b7~b0 is tp0~tp7 on/off status. 0 is key off, 1 is key on. figure 3-1. read operation sequence start condition p stop condition change data data or ack valid scl s sda figure 3-2. data transmission sequence address condition stop ack p 9 8 2 - 7 data 1 9 8 ack r/w 2 - 7 1 condition start s scl sda figure 3-3. a complete data transfer buf t su;sto r t r t t hd;sta t su;sta t f t f t su;dat t high t hd;sta t hd;dat t low t s p sr s scl sda figure 3-4. defini tion of timing for f/s-mode devices on the i 2 c-bus
preliminary TTP229-FSD tontouch tm 09?/12/22 page 8 of 14 ver : 1.1 table 3-2. characteristics of the s da and scl bus lines for f/s-mode i 2 c-bus devices standard-mode fast-mode parameter symbol min. max. min. max. unit scl clock frequency f scl 100 400 khz low period of the scl clock t low 4.7 1.3 us high period of the scl clock t high 4.0 0.6 us hold time (repeated) start condition t hd;sta 4.0 0.6 us set-up time for a repeated start condition t su;sta 4.7 0.6 us data hold time t hd;dat 0 0 us data set-up time t su;dat 250 100 ns rise time of both sda and scl signals t r 1000 300 ns fall time of both sda and scl signals t f 300 300 ns set-up time for stop condition t su;sto 4.0 0.6 us bus free time between a stop and start condition t buf 4.7 1.3 us capacitive load for each bus line c b 400 400 pf
preliminary TTP229-FSD tontouch tm 09?/12/22 page 9 of 14 ver : 1.1 4. key operating mode the TTP229-FSD has the single-key and mu lti-key functions. these functions are set by tp3 (skms1) and tp4 (skms0) pins. the all 8 keys can use one group, or th e 8 keys can distributed into two groups. the group-1 includes tp0, tp1, tp2, tp3 keys. th e group-2 includes tp4, tp5, tp6, tp7 keys. how to set the function? please see below table 4-1 table 4-1. the functions of tp3 (skms1) and tp4 (skms0) option tp3 (skms1) tp4 (skms0) operating function 1 1 all single-keys one group(8keys) 1 0 two groups operate group-1=>single key group-2=>single key 0 1 two groups operate group-1=>single key group-2=>multi key 0 0 all multi-keys one group(8 keys) note 1. one group tp0~tp7. two groups group-1=>tp0,tp1,tp2,tp3. group-2=>tp4,tp5,tp6,tp7. 2. the option states of tp3 and tp4, the 0 state is used a high-valu e resistor connected to vss, the 1 state is not used resist or connected to vss. 3. the key detection acknowledges in single-key function, the prior ity is by the key scanning order (from tp0 to tp7) when many keys ar e touched effectively. it is not by the key touching strength. 5. wake-up sampling rate and sampling length at sleep mode the TTP229-FSD has two kinds of sampling rate at sleep mode. these are 8hz and 64hz. the two functions are selected by tp5 (slwptm) pin. the tp5 (slwptm) pin has used a high-value resistor connected to vss, it selected the 64hz sampling rate . another it is 8hz that is not used resistor connected to vss. the 8hz sampling is the default. and TTP229-FSD has two kind s of sampling length at sleep mode . they are 4ms and 2ms that are selected by tp6 (wpsct) pin. the default is 4ms that tp6 (wpsct) pin is not used resistor connected to vss. another it is 2ms that tp6 pin has used a high-value resistor connected to vss. wake-up sampling timing and length in the sleep mode or 8hz=>125ms 4.0ms or 2.0ms 64hz=>15.6ms clock detect wake-up 6. maximum key-on time if some objects cover in the sense pad, and causi ng the change quantity enough to be detected. to prevent this, the TTP229-FSD sets a timer to monito r the detection. the timer is the maximum key-on time. it is set about 80sec at 3v. when the detect ion is over the timer, the system will return to the power-on initial state, and the output becomes inactiv e until the next detection. the function is set via a high-value resistor connected to the tp7 (sksrt) pin to vss. the tp7 (sksrt) pin does not has the resistor, it is set disable the maxi mum key-on time, then the key acts infinitely, this is the default. another it is set enable the maximu m key-on time that has a resistor.
preliminary TTP229-FSD tontouch tm 09?/12/22 page 10 of 14 ver : 1.1 7. built-in regulator the capacitive sensing touch pad ic needs stable power. so the TTP229-FSD built in regulator in the chip. it can make the internal power to keep up steady. a nd the sensitivity detect ion is normal for chip. and the stable power can avoid sensit ivity anomalies and false detections. 8. auto calibration function the TTP229-FSD includes a full auto-calibration func tion. after the device is powered-on, it will calibrate the initial condition of environment first. on the duration time all the functions are disabled, so do not operate. then the system is into stand- by mode. and all keys are not detected touch more than about 4 seconds, then the system do re-calib ration automatically. the procedure is fixed and repeated. by implementing this feature the system can catch the conditions of environment changing. and let operation of the system is normal. 9. the timing from sleep mode to operation mode re-calibration period period detect wake-up sleep mode time is about 4sec time is about 4sec re-calibration key scanning false trigger sleep mode detected key-out trigger finger key scanning figure 9-1. the timing for false trigger valid trigger after detected key release and do not any trigger about 8sec about 4sec about 4sec sleep mode re-calibration re-calibration detected key-out period period detect wake-up sleep mode operation mode trigger finger key scanning figure 9-2. the timing for valid trigger
preliminary TTP229-FSD tontouch tm 09?/12/22 page 11 of 14 ver : 1.1 10. option table option table option pin option states feature remark tp3 (skms1) tp4 (skms0) 1 1 all single-keys one group(8keys) default 1 0 two groups operate group-1=>single key group-2=>single key 0 1 two groups operate group-1=>single key group-2=>multi key tp3 (skms1) tp4 (skms0) 0 0 all multi-keys one group(8 keys) 1 8hz sampling rate for wake -up in sleep mode default tp5 (wpsct) 0 64hz sampling rate for wake-up in sleep mode 1 wake-up sampling length=>about 4.0ms default tp6 (slwptm) 0 wake-up sampling length=>about 2.0ms 1 maximum key-on time disable=>infinite default tp7 (sksrt) 0 maximum key-on time enable=>about 80sec note 1. about the combinations of group-1 and group-2, please see above point-4. 2. option states ?1? mean internal pull-up (default). 3. option states ?0? mean that option pi ns are via high-value re sistors connected to vss.
preliminary TTP229-FSD tontouch tm 09?/12/22 page 12 of 14 ver : 1.1 application circuit k0 k1 k3 k2 k7 k6 k5 k4 sksrt rp7 slwptm rp6 wpsct rp5 skms0 rp4 rp3 skms1 electrode cj0 cj1 vdd 104 c1 cjwa (ssop-20) ttp229-f a0 a1 a2 test vdd tp4 tp5 tp6 tp7 senadj1 scl tp0 tp1 sda tp2 tp3 senadj0 slpsena vss 11 12 13 14 16 17 18 19 20 15 4 3 5 6 7 8 9 10 2 1 ps 1. on pcb, the length of lines from t ouch pad to ic pin shorter is better. and the lines do not pa rallel and cross w ith other lines. 2. the power supply must be stable. if th e supply voltage drift or shift quickly, maybe causing sensitivity anomalies or false detections. 3. the material of panel covering on the pcb can not include the metal or the electric element. the paints on the surfaces are the same. 4. the c1 capacitor must be used between vdd and vss; and should be routed with very short tracks to the device?s vdd a nd vss pins (TTP229-FSD). 5. the capacitance cj0~cj1 and cjwa can be used to adjust the sensitivity. the value of capacitors use smaller, then the sensitivity will be better. the sensitivity adjustment must according to the practical application on pcb. the range value of capacitors are 1pf Q cj0~cj1 Q 50pf, 1pf Q cjwa Q 50pf. recommend to adjust the cj0~cj1 capacitor for k0~k7 first, then adjusting the cjwa capacitor for wake-up sensitivity. 6. the sensitivity adjustment capacitors (cj0~cj1, cjwa) must use smaller temperature coefficient and more stable capacitors. such are x7r, npo for example. so for touch application, recommend to use npo capacitor, for re ducing that the temperat ure varies to affect sensitivity. 7. recommend to use 820k ohm resistor for rp3~rp7 resistors.
preliminary TTP229-FSD tontouch tm 09?/12/22 page 13 of 14 ver : 1.1 package outline (20 pin ssop) package type: ssop-20 package outline dimension
preliminary TTP229-FSD tontouch tm 09?/12/22 page 14 of 14 ver : 1.1 order information a. package form: TTP229-FSD revise history 1. 2009/12/03 -original version v_1.0 2. 2009/12/22 =>v_1.1 -adding some descriptions for function. a. adding the description of stand-by current at the page-4. b. adding the description of single-ke y function at the page-9 point 4 note 3 . c. changing and adding the maximum key- on time value at the page-1, 3, 4, 9, 11. d. changing the description of table 4-1 at the page-9. e. changing the values for rp3~rp7 resi stors from 1m to 820k at page-12 ps: 7.

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